1. Field of the Invention
The present invention relates to processes involved in the manufacturing and testing of semiconductor devices. More particularly, the present invention relates to methods for detecting voltage spikes during testing of integrated circuits.
2. Description of the Related Art
As integrated circuit devices grow smaller and smaller, the testing of the integrated circuits presents greater challenges. For example, the shrinkage of transistor sizes to the point that critical dimensions are well below one micron (10−6 m), has compelled designers to reduce operating voltages to maintain device reliability. And while designers enjoy a significant improvement in device speeds due to the smaller geometries employed, it has not been possible to reduce power consumption in direct relation to those critical dimensions. As a result, device currents have tended to increase, which has forced designers to employ ever-greater amounts of ingenuity to the problem of distributing the total current available to the designed devices.
Unfortunately, this trend has resulted in electronic circuits becoming much more susceptible to power supply transient spikes (i.e., overvoltage conditions) which not only interfere with the proper function of latches and other devices, but can also deprive sufficient current to other areas of the circuit that are remote from the portion causing the spike (i.e., undervoltage or voltage droop conditions).
It is also important to distinguish between design-related problems and manufacturing-related problems. Manufacturing related problems relate primarily to quality issues and are the focus of specialized testing methods such as determined by automated testing techniques. In a traditional automated test equipment (ATE) environment, power and ground connections are required to be connected to the die under test but are inferior to those in the final application. This is a consequence of the need for quick-release capability in the test site coupled with the great physical distance between the device under test and the power supply that provides its power. The power supply voltage is commonly designated as VDD and may vary as it is distributed throughout the circuit, in part based on the demands placed on that particular part of the circuit.
The configuration of the testing environment typically increases this variation. In the testing environment, the soldering and desoldering of power, signal, and ground connections is not feasible because of the impact on testing throughput. Thus, these unique testing conditions may result in the manifestation of undervoltage or overvoltage measurements that are not reliably predictive of similar results in field operation of the circuit. That is, there may be a decrease in supplied voltage, i.e., VDD droop situations, that occur during testing that would never occur in the final application.
The traditional solution to this problem in manufacturing has been to change the decoupling on the device. That is, decoupling capacitors are used to buffer the voltages, sinking current during a positive voltage spike and supplying current during a negative voltage spike. But implementing decoupling changes that will satisfactorily address the varying current demands is difficult, and there are often very severe limits to the total bulk capacitance that can be added to a circuit before operation of the circuit is adversely affected. For example, sense lines for the power supply may enter into an oscillatory mode from excessive decoupling added to a circuit.
What is needed in this case, therefore, is a tool that can be easily used in manufacturing, and which will allow the manufacturing test engineers to pinpoint the precise locations where better decoupling is needed, and the locations where the designed decoupling should be placed for best effect. Specifically, it would be advantageous to provide a method for incrementally changing decoupling and then evaluating the consequences of that change in detail. This will greatly reduce the number of false starts in trying to reduce noise in the design and will allow the manufacturing support engineers to minimize the total decoupling that is used on the design. Since total decoupling always has a marginal effect on test speed (from power-on speed on settling time after voltage changes), such a minimization would provide direct cost benefits in manufacturing as well.
A second area where VDD droop problems occur is the design itself. Even in cases where the ATE test environment is fairly close to ideal, the power routing within the integrated circuit itself may prevent proper operation of the circuit under all field conditions. For example, in some cases the design shows no problems in simulations but does so in field operation. These situations often require the expensive and time-consuming steps of micro-probing the circuit to identify the regions prone to VDD drop or current starvation. Even after undertaking these measures, the results are still prone to error.
Thus, a non-invasive method of testing the VDD levels inside a device at some arbitrary point in time during testing as well as field operations of the circuit would be extremely useful. These methods should permit determination of over and undervoltages accurately under various conditions.